Register file

A register file is an array of addressable registers which has two or more ports that allow concurrent reading and writing of registers in the array. Reading is nondestructive, meaning that the act of reading does not alter the stored data.

Each port is either a write port or a read port, with input and output signals relevant to the port function. All ports have address inputs that specify the register to be accessed. Write ports also have data inputs that specify the value to be written to the register, and a write enable input that allows the data to be written. Read ports have data outputs that convey the register's output value.

Register files are used in a variety of applications, including as processor registers in central processing units (CPUs), as data memory in FIFOs, and in hardware accelerators.

Typical architecture

Simultaneous read/write

Depending on its design and, if applicable, its configuration, a register file will behave in one of several ways when a read port and write port simultaneously access the same register. More specifically, the read port will output either the newly written data (commonly referred to as forwarding or bypassing), or the currently stored data (sometimes called read before write), or undefined data.

Write arbitration

Most register files make no special provisions to prevent multiple write ports from writing to the same register simultaneously. Instead, it is usually the responsibility of external circuitry to ensure simultaneous writes do not occur.

Applications

Central processing units (CPUs)

The program-accessible registers in a CPU's register file are defined by the CPU's instruction set architecture. The register width (number of bits) typically matches the processor word width, though in same cases additional bits are provided to accommodate addresses larger than the processor word or for other purposes.

Depending on the CPU design, registers may be directly addressed by instructions or they may be dynamically mappable. The latter may involve register renaming, register banking, windowing, or combinations of these.

In the physical layout, the wire pitch area increases as the square of the number of ports,Johan Janssen. "Compiler Strategies for Transport Triggered Architectures". 2001. p. 169, 171-173 and consequently as the number of read ports increases, at some point multiple redundant register files with fewer read ports may be faster or smaller (or both) than a single register file. This is typically implemented by means of distributed or partitioned register files.

Register-bank switching Some processors have multiple physical register files, with each file treated as a bank of registers within a single, larger memory space.Wikibooks: Microprocessor Design/Register File#Register Bank Examples of this include MODCOMP and 8051-compatible processors, which use program status word bits to select the active register bank, and ARM processors, in which the physical registers associated with banked registers R8 to R14 depend on the processor's operating mode.

Shadow registers

The physical layout area can sometimes be reduced by using two smaller data paths side-by-side, which usually results in a "shadow register" architecture consisting of multiple copies of a register file, one for each data path. Examples of this include the Alpha 21264 (EV6) with two copies of the register files, and SPARC with up to four copies.

Register renaming Processors that perform register renaming can arrange for each functional unit to write to a subset of the physical register file, thus eliminating the need for multiple write ports per cell. An example of this is the R10000, which employs a register renaming mapping file to store a virtual register number for each of its physical registers.

Some processors employ register windowing to map program-specified register numbers to a contiguous region within a larger physical register file. For example, in SPARC processors, the five-bit register numbers act as pointers to a 32-word region of a larger register file. Some processors implement this as a register file composed of multi-bit "cells" in which one bit is accessible to the ports; the bits can be rotated, thus effectively switching to a different window.

See also Sum-addressed decoder Hardware register

References

External links

Register file

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