An instruction set architecture (ISA) is an abstract model that defines the programmable interface of the CPU of a computer, defining how software interacts with hardware. A device (i.e. CPU) that interprets instructions described by an ISA is an implementation of that ISA. Generally, the same ISA is used for a family of related CPU devices.
In general, an ISA defines the instructions, data types, registers, and the programming interface for managing main memory such as addressing modes, virtual memory, and memory consistency mechanisms. The ISA also includes the input/output model of the programmable interface.
An ISA specifies the behavior implied by machine code running on an implementation of that ISA in a fashion that does not depend on the characteristics of that implementation, providing binary compatibility between implementations. This enables multiple implementations of an ISA that differ in characteristics such as performance, physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the microarchitectures of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations.
If an operating system maintains a standard and compatible application binary interface (ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system.
An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute machine code for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions.
The binary compatibility that they provide makes ISAs one of the most fundamental abstractions in computing.
Overview An instruction set architecture is distinguished from a microarchitecture, which is the set of processor design techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but they have radically different internal designs.
The concept of an architecture, distinct from the design of a specific machine, was developed by Fred Brooks at IBM during the design phase of System/360.
Some virtual machines that support bytecode as their ISA such as Smalltalk, the Java virtual machine, and Microsoft's Common Language Runtime, implement this by translating the bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see: Just-in-time compilation). Transmeta implemented the x86 instruction set atop very long instruction word (VLIW) processors in this fashion.
Classification of ISAs
An ISA may be classified in a number of different ways. A common classification is by architectural complexity. A complex instruction set computer (CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A reduced instruction set computer (RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.
Other types include VLIW architectures, and the closely related and explicitly parallel instruction computing (EPIC) architectures. These architectures seek to exploit instruction-level parallelism with less hardware than RISC and CISC by making the compiler responsible for instruction issue and scheduling.
Architectures with even less complexity have been studied, such as the minimal instruction set computer (MISC) and one-instruction set computer (OISC). These are theoretically important types, but have not been commercialized.
Instructions Machine language is built up from discrete statements or instructions. On the processing architecture, a given instruction may specify: opcode (the instruction to be performed) e.g. add, copy, test any explicit operands: registers literal/constant values addressing modes used to access memory More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by control flow instructions.
Instruction types Examples of operations common to many instruction sets include:
Data handling and memory operations Set a register or memory to a fixed constant value. Copy data from a one place to another. This operation is often called load or store. Although the machine instruction is often called move, the term is misleading because the source remains unchanged. These operations are used to store the contents of a register, the contents of another memory location or the result of a computation, or to retrieve stored data to perform a computation later. Read or write data from hardware devices.
Arithmetic and logic operations Add, subtract, multiply, or divide the values of two registers, placing the result in a register, possibly setting one or more condition codes in a status register. , in some ISAs, saving operand fetch in trivial cases. Perform bitwise operations, e.g., taking the conjunction and disjunction of corresponding bits in a pair of registers, taking the negation of each bit in a register. Compare two values in registers (for example, to see if one is less, or if they are equal). s for arithmetic on floating-point numbers.
Control flow operations Branch to another location in the program and execute instructions there. Conditionally branch to another location if a certain condition holds. Execute an instruction at another location and continue at the next instruction following the execute. Indirectly branch to another location. Repeat an instruction a specified number of times Select an instruction counter on a machine that has multiple instruction counters, e.g., Sequence Counter versus Cosequence counter on the Honeywell 800. Skip one or more instructions, depending on conditions (a conditional branch a fixed number of instructions forward) Trap Explicitly cause a software interrupt, either conditionally or unconditionally. Call another block of code, while saving the context of the next instruction as a point to return to. Return from a previous call by retrieving the saved context.
Coprocessor instructions Load/store data to and from a coprocessor or exchanging with CPU registers. Perform coprocessor operations. Some examples of coprocessor instructions include those for the IBM 3090 Vector facility and the Intel 8087.
Elaborate instructions Processors may include elaborate instructions in their instruction set. A single elaborate instruction does something that may require many instructions or a subroutine on other computers. Such instructions are typified by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor. Some examples of elaborate instructions include:
transferring multiple registers to or from memory (especially the stack) at once moving large blocks of memory (e.g. string copy) searching strings for matches or differences arithmetic on BCD strings complicated integer and floating-point arithmetic (e.g. square root, or transcendental functions such as logarithm, sine, cosine, etc.) s, a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicated SIMD registers
Elaborate instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC instruction sets include SIMD or vector instructions that perform the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy parallelization of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as MMX, 3DNow!, and AltiVec.
Instruction encoding
On traditional architectures, an instruction includes an opcode that specifies the operation to perform, such as add contents of memory to register—and zero or more operand specifiers, which may specify registers, memory locations, or literal data. The operand specifiers may have addressing modes determining their meaning or may be in fixed fields. In very long instruction word (VLIW) architectures, which include many microcode architectures, multiple simultaneous opcodes and operands are specified in a single instruction.
Some exotic instruction sets, such as transport triggered architectures (TTA), do not have an opcode field only operand(s).
Most stack machines have "0-operand" instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix (reverse Polish notation) operations that work only on the expression stack, not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.
Conditional instructions
Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and the target location not modified, if the condition is false. Similarly, IBM z/Architecture has a conditional store instruction. A few instruction sets include a predicate field in every instruction. Having predicates on instructions is called predication, and can include conditional-branches, such as on the SuperH.
Loop control instructions Many architectures have conditional branch instructions designed for controlling loops. Typically, they update and test a register. Examples include
IBM 7070 Branch decremented index word (BDX) Branch incremented index word (BIX) IBM 7090 Transfer on index (TIX) Transfer on index high (TXH) Transfer on index low or equal (TXL) IBM System/360 Branch on count (BCT, BCTR) Branch on index high (BXH) Branch on index low or equal (BXLE) PDP-11 Subtract one and branch (SOB) Zilog Z80 Decrement jump not zero (DJNZ)
Number of operands Instruction sets may be categorized by the maximum number of operands explicitly specified in instructions.