Wafer (Electronics)A real, fully processed monolithic silicon semiconductor wafer patterned with individual integrated circuit dies.Alternative namesSlice, substratePrimary purposeBase substrate for monolithic integrated circuits and photovoltaicsCommon materialsSilicon (c-Si), Gallium arsenide (GaAs), Silicon carbide (SiC), Gallium nitride (GaN), Indium phosphide (InP)Geometric Standards & SizesState-of-the-art diameter300 mm (12 in) • 450 mm (experimental)Legacy & specialized sizes200 mm (8 in), 150 mm (6 in), 100 mm (4 in)Typical thickness775 μm (for 300 mm) • 725 μm (for 200 mm)Surface roughness ($R_a$)< 0.1 to 0.2 nm (Atomically specular polish)Crystallographic AttributesCrystal structureDiamond cubic (for Silicon) • Zincblende / Wurtzite (for III-V compounds)Miller indices / Orientation{100} (Standard logic/CMOS) • {111} (Bipolar, power devices, MEMS)Orientation alignmentPrimary/Secondary flats (≤200 mm) • Notches (300 mm+)Primary Substrate ManufacturingCrystal growth techniqueCzochralski method (CZ for ICs) • Float-Zone (FZ for high-purity/power RF)Ingot slicing methodDiamond wire sawing (DWS)Mechanical sizingEdge profiling/rounding (Prevents stress concentrations and chipping)Surface preparationChemical etching (Removes sawing damage) • Chemical-mechanical planarization (CMP)Mechanical & Material Constants (Silicon)Young's modulus ($E$)~130 GPa ({100} plane) to ~185 GPa ({111} plane)Poisson's ratio ($\nu$)~0.22 to 0.28 (Anisotropic)Lattice parameter ($a$)5.4307 Å (0.54307 nm) at 300 KIntrinsic bow / warpWarp < 30 μm (Critical for Photolithography depth of focus)

In electronics, a wafer (also called a slice or substrate) is a thin slice of semiconductor, such as a crystalline silicon (c-Si, silicium), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells.

The wafer serves as the substrate for microelectronic devices built in and upon the wafer. It undergoes many microfabrication processes, such as doping, ion implantation, etching, thin-film deposition of various materials, and photolithographic patterning. Finally, the individual microcircuits are separated by wafer dicing and packaged as an integrated circuit.

History

In the semiconductor industry, the term wafer appeared in the 1950s to describe a thin round slice of semiconductor material, typically germanium or silicon. The round shape characteristic of these wafers comes from single-crystal ingots usually produced using the Czochralski method. Though, silicon wafers were first introduced in the 1940s.

By 1960, silicon wafers were being manufactured in the U.S. by companies such as MEMC and SunEdison. In 1965, American engineers Eric O. Ernst, Donald J. Hurd, and Gerard Seeley, while working under IBM, filed Patent US3423629A for the first high-capacity epitaxial apparatus.

Production

Formation

Wafers are formed of highly pure,SemiSource 2006: A supplement to Semiconductor International. December 2005. Reference Section: How to Make a Chip. Adapted from Design News. Reed Electronics Group. nearly defect-free single crystalline material, with a purity of 99.9999999% (9N) or higher. One process for forming crystalline wafers is known as the Czochralski method, invented by Polish chemist Jan Czochralski. In this process, a cylindrical ingot of high purity monocrystalline semiconductor, such as silicon or germanium, called a boule, is formed by pulling a seed crystal from a melt. Donor impurity atoms, such as boron or phosphorus in the case of silicon, can be added to the molten intrinsic material in precise amounts in order to dope the crystal, thus changing it into an extrinsic semiconductor of n-type or p-type.

The boule is then sliced with a wafer saw (a type of wire saw), machined to improve flatness, chemically etched to remove crystal damage from machining steps and finally polished to form wafers. The size of wafers for photovoltaics is 100–200 mm square and the thickness is 100–500 μm. Electronics use wafer sizes from 100 to 450 mm diameter. The largest wafers made have a diameter of 450 mm, but are not yet in general use.

Cleaning, texturing and etching

Wafers are cleaned with weak acids to remove unwanted particles. There are several standard cleaning procedures to make sure the surface of a silicon wafer contains no contamination. One of the most effective methods is the RCA clean. When used for solar cells, the wafers are textured to create a rough surface to increase surface area and so their efficiency. The generated PSG (phosphosilicate glass) is removed from the edge of the wafer in the etching.

Wafer properties

Standard wafer sizes Silicon substrate Silicon wafers are available in a variety of diameters from 25.4 mm (1 inch) to 300 mm (11.8 inches). Semiconductor fabrication plants, colloquially known as fabs, are defined by the diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab using , with a proposal to adopt .Presentations/PDF/FEP.pdf ITRS Presentation (PDF) Intel, TSMC, and Samsung were separately conducting research to the advent of "prototype" (research) fabs, though serious hurdles remain.

Wafer size Typical thickness Year introduced Weight per wafer 100 mm2 die per wafer 1960 275 μm 19699 375 μm 197229 525 μm 1976 10 grams 56 4.9 inch (125 mm) 625 μm 198195 150 mm (5.9 inch, usually referred to as "6 inch") 675 μm 1983144 200 mm (7.9 inch, usually referred to as "8 inch") 725 μm. 1992 53 grams 269 300 mm (11.8 inch, usually referred to as "12 inch") 775 μm 1999 125 grams 640 450 mm (17.7 inch) (proposed) 925 μm – 342 grams 1490 675 mm (26.6 inch) (theoretical) unknown – unknown 3427 Wafers grown using materials other than silicon will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the material used; the wafer must be thick enough to support its own weight without cracking during handling. The tabulated thicknesses relate to when that process was introduced, and are not necessarily correct currently, for example the IBM BiCMOS7WL process is on 8-inch wafers, but these are only 200 μm thick. The weight of the wafer increases with its thickness and the square of its diameter. Date of introduction does not indicate that factories will convert their equipment immediately, in fact, many factories do not bother upgrading. Instead, companies tend to expand and build whole new lines with newer technologies, leaving a large spectrum of technologies in use at the same time.

Gallium Nitride substrate GaN substrate wafers typically have had their own independent timelines, parallel but far lagging silicon substrate, but ahead of other substrates. The world's first 300 mm wafer made of GaN was announced in Sept 2024 by Infineon, suggesting in the coming future they could put into use the first factory with 300 mm GaN commercial output.

SiC substrate Meanwhile world's first Silicon Carbide (SiC) 200 mm wafers were announced in July 2021 by ST Microelectronics. It is not known if SiC 200 mm has entered volume production as of 2024, as typically the largest fabs for SiC in commercial production remain at 150 mm.

Silicon on sapphire Silicon on sapphire (SOS) is a specific type of Silicon on Insulator (SOI) technology, where the insulating substrate is sapphire and the active superstrate is silicon. Epitaxial layers and doping can be tailored as needed. SOS in commercial production is typically maxed out at 150 mm wafer sizes as of 2024.

Gallium Arsenide substrate GaAs wafers tend to be 150 mm at largest, in commercial production as of 2024.

Aluminum Nitride substrate AlN tends to be 50 mm or 2 inch wafers in commercial production, while 100 mm or 4 inch wafers are being developed as of 2024 by wafer suppliers like Asahi Kasei. However, merely because a wafer exists commercially, does not imply in any way that processing equipment to produce chips on that wafer exists, indeed such equipment tends to lag development until paying end customer demand materializes. Even after equipment is developed (years), it can take further years for fabs to figure out how to use the machines productively.

Diamond substrate Diamond tends to be 50-55 mm or ~2 inch wafers in prototype production, while commercial production is being targeted as of 2026.

Historical increases of wafer size A unit of wafer fabrication step, such as an etch step, can produce more chips proportional to the increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer area. This was the cost basis for increasing wafer size. Conversion to 300 mm wafers from 200 mm wafers began in early 2000, and reduced the price per die for about 30–40%.Larger diameter wafers allow for more die per wafer.

Photovoltaic

M1 wafer size (156.75 mm) is in the process of being phased out in China as of 2020. Various nonstandard wafer sizes have arisen, so efforts to fully adopt the M10 standard (182 mm) are ongoing. Like other semiconductor fabrication processes, driving down costs has been the main driving factor for this attempted size increase, in spite of the differences in the manufacturing processes of different types of devices.

Crystalline orientation

Wafers are grown from crystal having a regular crystal structure, with silicon having a diamond cubic structure with a lattice spacing of 5.430710 Å (0.5430710 nm). When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the Miller index with (100) or (111) faces being the most common for silicon. Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic. Ion implantation depths depend on the wafer's crystal orientation, since each direction offers distinct paths for transport.

Wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("dies") so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.

Crystallographic orientation notches

Wafers under 200 mm diameter have flats cut into one or more sides indicating the crystallographic planes of the wafer (usually a {110} face). In earlier-generation wafers a pair of flats at different angles additionally conveyed the doping type (see illustration for conventions). Wafers of 200 mm diameter and above use a single small notch to convey wafer orientation, with no visual indication of doping type. 450 mm wafers are notchless, relying on a laser scribed structure on the wafer surface for orientation.

Impurity doping

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 1013 and 1016 atoms per cm3 of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer as either bulk n-type or p-type. However, compared with single-crystal silicon's atomic density of 5×1022 atoms per cm3, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum. Transition metals, in particular, must be kept below parts per billion concentrations for electronic applications.

450 mm wafers

Challenges